Memory tests on semiconductor devices, such as random access memory devices, are typically performed by the manufacturer during fabrication to locate defects and failures in the devices that can occur during the fabrication of the device. This testing is typically performed by a processor which runs a testing program before the die containing the semiconductor device is packaged into a chip. Many semiconductor devices including memory devices typically have redundant circuitry to replace malfunctioning circuitry found during testing. By enabling the redundant circuitry, the device need not be discarded even if some of the circuits are defective.
As memory size increases, the time required to test a DRAM being manufactured must increase as well, resulting in additional cost. Also, as DRAM applications grow and processors begin to incorporate large quantities of memory on chip, it is necessary to create new testing schemes for these embedded memories. When there is no direct connection between pins and memory, external testing can be difficult. That is, ensuring that every bit is tested thoroughly requires complex test vectors.
Built in self testing (BIST) Built in self testing enables cheaper testing equipment to be used to test the memory device, as well as parallel testing which can increase chip production rates. Finally, built in self tests can, in some cases, be performed throughout the operational life of the chip. However, conventional methods for determining defects in a semiconductor device are complex and can be time consuming.
Accordingly, there is a need for a memory device and method of determining defects in a semiconductor device by scanning the memory array to locate the word lines and column select lines with the highest number of defects and by storing fail addresses of a memory cell.